Syllabus

1. Design and hardware implementation of: 
   a. 2-bit Adder/Subtractor with XOR as well as NAND gates,
   b. 4:1 Multiplexer using universal gates and realization of Full Adder using Multiplexers,
   c. BCD Adder using two binary adders (IC based) and other gates,
   d. 3:8 Decoder and realization of Full Adder.
2. Realization of R-S, D and J-K latches and D Flip-Flop.
3. Realization of Mod-8 Up-Down Ripple Counter.
4. Realization of synchronous Mod-3 and Mod-2 counters.
5. Realization of higher Mod counter by cascading lower Mod counters PART II: Digital System Design using HDL and EDA.
6. Modeling different types of gates: (a) 2-input NAND (b) 2-input OR gate (c) 2-input NOR gate (d) NOT gate (e) 2-input XOR gate (f) 2-input XNOR gate.
7. Modeling (a) Half-adder (b) Full-adder.
8. Modeling a “D flip-flop”.
9. Modeling a “D Latch”.
10. Modeling a (a) 2-to-1 Multiplex (b) 2-to-4 Decoder (c) Tri-State Buffer.
11. Modeling a 4-to-1 Multiplexer.
12. Modeling a 4-bit PARALLEL ADDER.
13. Modeling a 4-bit adder-subtractor circuit