Classical scaling in CMOS, Moore’s Law, Clean room concept, Material properties, crystal structure, lattice, characterization of material based on band diagram and bonding, conductivity, resistivity, sheet resistance, phase diagram and solid solubility.
Growth of single crystal Si, Wafer Cleaning and etching-Wet etch, Dry etch, Plasma etching, RIE etching, etch selectivity/selective etch, Lithography (Photolithography, EUV lithography, X-ray lithography, e-beam lithography etc.) Next generation technologies: Immersion lithography, Phase shift mask, ion lithography, SCALPEL.
Thermal oxidation-Kinetics, Characterization of oxide films, High k and low k dielectrics for ULSI Impurity incorporation: Solid State diffusion modeling and technology, Ion Implantation modeling, technology and damage annealing, characterization of Impurity profiles, Deposition & Growth (PVD, CVD, ALD, epitaxy, MBE, ALCVD etc.),Metal film deposition: Evaporation and sputtering techniques.
Planarization Techniques: Need for planarization, Chemical Mechanical Polishing Process integration for NMOS CMOS and Bipolar circuits, Back end of line processes (Copper damascene process, Metal interconnects; Multi-level metallization schemes) Advanced MOS Technologies.
James Plummer, M. Deal and P.Griffin, Silicon VLSI Technology, Prentice Hall Electronics
Stephen Campbell, The Science and Engineering of Microelectronics, Oxford University Press, 1996
S.M. Sze (Ed), VLSI Technology, 2nd Edition, McGraw Hill, 1988
C.Y. Chang and S.M.Sze (Ed), ULSI Technology, McGraw Hill Companies Inc, 1996.
S.K. Ghandhi, VLSI Fabrication Principles, John Wiley Inc., New York, 1983.
Course Outcomes (COs):
CO1: Understand advance transistors and related devices followed by scaling rules for modern CMOS.
CO2: Analyze short channel devices, and realize CMOS
CO3: Understand CMOS process and evaluation of technology from generation to generation.
CO4: Ability to read and analysis the recent journals regarding the development of VLSI technology.